IFPGA.h

/*
 * This file is part of LSST M1M3 support system package.
 *
 * Developed for the Vera C. Rubin Telescope and Site System.
 * This product includes software developed by the LSST Project
 * (https://www.lsst.org).
 * See the COPYRIGHT file at the top-level directory of this distribution
 * for details of code ownership.
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <https://www.gnu.org/licenses/>.
 */
 
#ifndef LSST_M1M3_SS_FPGA_IFPGA_H_
#define LSST_M1M3_SS_FPGA_IFPGA_H_
 
#include <cRIO/FPGA.h>
 
#include <HealthAndStatusFPGAData.h>
#include <SupportFPGAData.h>
 
namespace LSST {
namespace M1M3 {
namespace SS {

class IFPGA : public cRIO::FPGA {
public:
    IFPGA() : cRIO::FPGA(cRIO::SS) {}
    virtual ~IFPGA() {}
 
    static IFPGA &get();
 
    uint16_t getTxCommand(uint8_t bus) override;
    uint16_t getRxCommand(uint8_t bus) override;
    uint32_t getIrq(uint8_t bus) override;

    SupportFPGAData *getSupportFPGAData() { return &supportFPGAData; }

    HealthAndStatusFPGAData *getHealthAndStatusFPGAData() { return &healthAndStatusFPGAData; }

    virtual void waitForOuterLoopClock(uint32_t timeout) = 0;

    virtual void ackOuterLoopClock() = 0;

    virtual void waitForPPS(uint32_t timeout) = 0;

    virtual void ackPPS() = 0;

    virtual void waitForModbusIRQs(uint32_t warning_timeout, uint32_t error_timeout) = 0;

    virtual void ackModbusIRQs() = 0;

    virtual void pullTelemetry() = 0;

    virtual void pullHealthAndStatus() = 0;

    virtual void writeTimestampFIFO(uint64_t timestamp) = 0;

    virtual void readU8ResponseFIFO(uint8_t *data, size_t length, uint32_t timeoutInMs) = 0;

    virtual void writeHealthAndStatusFIFO(uint16_t request, uint16_t param = 0) = 0;

    virtual void readHealthAndStatusFIFO(uint64_t *data, size_t length, uint32_t timeoutInMs = 10) = 0;

    virtual void readRawAccelerometerFIFO(uint64_t *raw, size_t samples) = 0;

    void setPower(bool aux, bool network);

    void setPower(const bool aux[4], const bool network[4]);
 
protected:
    SupportFPGAData supportFPGAData;
    HealthAndStatusFPGAData healthAndStatusFPGAData;
 
private:
    IFPGA &operator=(const IFPGA &) = delete;
    IFPGA(const IFPGA &) = delete;
};
 
} /* namespace SS */
} /* namespace M1M3 */
} /* namespace LSST */
 
#endif /* LSST_M1M3_SS_FPGA_IFPGA_H_ */